This invention is directed to methods of controlling operating characteristics of semiconductor devices, particularly NDR field-effect transistor devices which can be configured to operate adaptively in response to changing operational requirements.
Silicon based devices that exhibit a negative differential resistance (NDR) characteristic have long been sought after in the history of semiconductor devices. A new type of CMOS compatible, NDR capable FET is disclosed in the following King et al. applications:
Ser. No. 09/603,101 entitled xe2x80x9cA CMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAMExe2x80x9d; and
Ser. No. 09/603,102 entitled xe2x80x9cCHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODExe2x80x9d now issued as U.S. Pat. No. 6,479,862 on Nov. 12, 2002; and
Ser. No. 09/602,658 entitled xe2x80x9cCMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE;
all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein. The advantages of such device are well set out in such materials, and are not repeated here.
As also explained in such references, NDR devices can be used in a number of circuit applications, including multiple-valued logic circuits, static memory (SRAM) cells, latches, and oscillators to name a few. The aforementioned King et al. applications describe a break-through advancement that allows NDR devices to be implemented in silicon-based IC technology, using conventional planar processing techniques as for complementary metal-oxide-semiconductor (CMOS) FET devices. The integration of NDR devices with CMOS devices provides a number of benefits for high-density logic and memory circuits.
It is clear, from the advantages presented by the above-described NDR device, that overall improvements in manufacturing, testing and operation of the same are desirable to refine and proliferate such technologies.
In addition, enhancements in trap location control, trap energy level control, and trap formation, are also useful for these types of NDR devices, and could be beneficial to other types of trap-based devices as well.
Furthermore, the prior art to date has been limited generally to devices in which the peak-to-valley ratio (PVR) is not easily adjustable. It would be useful, for example, to be able to control the PVR directly during manufacture, so as to permit a wide variety of NDR behaviors for different circuits on a single die/wafer. Alternatively, the ability to control PVR during normal operation of a device would also be useful, but is generally not possible with current NDR technologies.
The object of the present invention, therefore, is to address the aforementioned limitations in the prior art, and to provide additional embodiments of trapping devices, NDR devices, and methods of making, operating and testing the same. These and other objects are accomplished by various embodiments of the present invention as described in detail below, it being understood by those skilled in the art that many embodiments of the invention will not use or require all aspects of the invention as described herein.
A first aspect of the invention, therefore, concerns a method of forming a silicon based negative differential resistance (NDR) field effect transistor (FET) comprising the preferred steps of: providing a substrate; forming a first NDR region for the NDR FET over a first portion of the substrate using a first impurity, the first NDR region being adapted for imparting an NDR characteristic to the NDR FET; placing a second impurity in the first portion of the substrate to adjust a threshold voltage characteristic of the NDR FET; performing a first thermal treatment operation for the NDR FET after the above are completed; forming a gate insulating layer for the NDR FET over the first portion of the substrate; performing a second thermal treatment operation for the NDR FET; forming a gate electrode for the NDR FET; forming a source region and a separate drain region for the NDR FET adjacent to the gate electrode, the source region and drain region being coupled through an NDR FET channel located in the first portion of the substrate.
In this manner, an NDR FET preferably operates with a negative differential resistance characteristic when sufficient charge carriers from the channel are temporarily trapped in the first NDR region. The first impurity is preferably a first type dopant, and the second impurity is preferably a second type dopant which is opposite to the first type dopant. The first thermal treatment operation is preferably performed with a furnace, while the second thermal treatment operation is preferably performed with a rapid thermal anneal lamp in a pulsed heated chamber. Furthermore, in addition to the above, a third thermal treatment operation is preferably performed after the gate electrode is formed.
In later steps, a silicide contact to the gate electrode and/or one or both of the source region and the drain region can be formed.
Some embodiments of the invention, therefore, are silicon based negative differential resistance (NDR) field effect transistor (FET) which have a peak-to-valley current ratio (PVR) that exceeds ten (10) over a temperature range of 50xc2x0 C. In some instances, a PVR can exceed one thousand (1000) over a temperature range of 100xc2x0 C.
In other embodiments, a silicon on insulator (SOI) substrate is used; a variety of substrates are suitable for the present invention, including strained Si or silicon carbide (SiC).
The impurities added to the FET are used to create charge trapping sites which preferably have an energy characteristic that is higher than a conduction band edge of the substrate.
In other embodiments, an NDR FET and a non-NDR FET are made at the same time using common manufacturing operations. For example, isolation regions, LDD implants, gate insulators, gate electrodes, contacts, source/drain implants, etc., can be done using a shared processing step. In such instances, an NDR region for an NDR device is preferably constructed from a gate insulator region for an NDR FET.
In still other embodiments, two different types of NDR devices can be formed in a common substrate. Thus, a second NDR region for another NDR element is formed over a second region of the semiconductor substrate, the second NDR region being adapted for imparting a second NDR characteristic different from an NDR characteristic for a first NDR FET.
A related aspect of the invention, therefore, pertains to a charge-trap based negative differential resistance (NDR) element which operates with an NDR characteristic defined by a peak current and a valley current. By appropriate distribution of charge traps in a trapping region of the NDR element, including controlling a concentration and energy of the same, a peak-to-valley current ratio (PVR) for the NDR element can be imparted which exceeds ten (10) over a temperature range spanning 50xc2x0 C.
In other embodiments the PVR can be constructed to vary by less than a factor of five in an operating temperature spanning 25xc2x0 C. and 125xc2x0 C. In still other embodiments, the PVR exceeds 1000 in an operating temperature spanning 25xc2x0 and 125xc2x0. The trapping region preferably forms an interface with a channel of a field effect transistor associated with the NDR element.
Other embodiments of charge trapping devices can be similarly constructed to achieve similar performance.
Another aspect of the invention concerns a method of forming a negative differential resistance (NDR) device comprising the steps of: forming a gated silicon-based NDR element; and setting a peak-to-valley ratio (PVR) characteristic of the gated silicon-based NDR element during manufacture of the silicon-based semiconductor transistor to a target PVR value located in a range between a first PVR value and a second PVR value. Thus, a target PVR value can be varied during manufacturing of the NDR device within a semiconductor process such that the NDR device can be configured to have a PVR value ranging between a first usable PVR value and a second usable PVR value, where the first usable PVR value and the second PVR value vary by at least a factor of ten (10).
In some instances, a desired PVR value can be set using a single processing operation, such as an implant.
A preferred approach uses only metal oxide semiconductor (MOS) compatible processing operations. The inventive process is flexible enough so that within a particular manufacturing facility, a first semiconductor substrate on a first wafer and a second separate semiconductor substrate on a second wafer can have different target PVR values imparted at different times. The different PVR values can be programmed into a semiconductor processing apparatus such as an implanter, a furnace, an anneal chamber, a deposition system, etc. An NDR voltage onset point (VNDR) is also preferably set during manufacture.
In still other more specific embodiments, a PVR (and/or a VNDR) value can be set during manufacture by controlling one or more general process parameters.
For example, in some embodiments, a PVR and/or VNDR can be set during manufacture by controlling a thickness of a gate insulator grown for the NDR device. In particular, a PVR characteristic can be increased simply by increasing a thickness of the gate insulator. The gate insulator is preferably at least 5 nm thick, and can be a single layer, or a composite of two different materials. In some applications the gate will include both a thermal oxide and a deposited oxide based material. Thus, it is possible in some applications to have a common substrate that includes a silicon based NDR device with a first PVR characteristic using a first gate insulator thickness and a second silicon based NDR device with a second PVR characteristic using a second gate insulator thickness.
In another embodiment, a PVR and/or VNDR can be set during manufacture by controlling a channel length used for a silicon based NDR FET. Because the present invention scales very well, a PVR characteristic tracks a channel length, so that a higher PVR can be achieved by using a smaller channel, and a lower PVR can be achieved by using a longer channel. Accordingly, PVR characteristics can be established through conventional masking operations which define a channel length, and/or which define a source/drain region implant. The channel can also have a size that is defined by a variable sized spacers deposited on the sidewalls of a gate electrode. Thus, a PVR value can be increased significantly through even small reductions in channel lengths.
In still another embodiment, a PVR and/or VNDR can be set during manufacture by controlling an impurity species and/or impurity dose introduced into a charge trapping layer associated with the NDR element to match a target charge trap profile. In a a preferred approach Boron is selected as the impurity at a dose ranging from 1*1014/cm2 to 3*1014 atoms/cm2. This results in a target charge trap profile in which a concentration of charge traps is greater than about 1*1019 atoms/cm3 at a trapping region of the charge trapping layer, and less than about 1*1018 atoms/cm3 at a bulk region of the charge trapping layer. A PVR can thus be altered merely by selecting another impurity, another dosage, etc. For example, increasing an impurity dose of Boron by 50% can result in an increase of greater than 100% in a PVR characteristic. As with the other PVR processing embodiments, an NDR voltage onset point (VNDR) can also be controlled in this fashion.
In still another embodiment, a PVR and/or VNDR can be set during manufacture by controlling an overall trap distribution, such as a target location of the charge traps and a target concentration of the charge traps. In a preferred embodiment, the charge traps are distributed within a target location is a region that is less than about 0.5 nm thick. Furthermore, a concentration of traps is arranged so that an interface concentration is least an order of magnitude greater than in bulk areas of the charge trapping layer.
In other embodiments, a PVR and/or VNDR can be set during manufacture by controlling a rapid thermal anneal (RTA) operation. A preferred approach is to use a cycle at a temperature that exceeds 1000xc2x0 C. for at least part of the cycle in a conventional lamp based chamber. This type of operation serves to focus and concentrate charge traps at a channel interface region, as opposed to bulk regions.
In still other embodiments, a PVR and/or VNDR can be set during manufacture by controlling a lightly doped drain operation, including an implant species and/or dosage. performed during formation of a lightly doped drain region operation. In a preferred embodiment, arsenic is used as the dopant species at a dosage in excess of 1*1015 atoms/cm2 to effectuate the implant operation. In other embodiments, phosphorus is used as the dopant species at a dosage in excess of 1*1015 atoms/cm2 to effectuate the implant operation. Since Arsenic achieves a PVR that is at least 2 times greater than Phosphorus, it is preferred for those applications where PVR is more critical to the operation of a circuit.
Related aspects of the invention concern a semiconductor processing apparatus for manufacturing a negative differential resistance (NDR) device on a silicon wafer which can be programmed to tailor a specific PVR value on a wafer by wafer basis (or even die by die). The apparatus is preferably located in a conventional semiconductor fab, and includes a programmable controller responsive to a negative differential resistance (NDR) related process recipe associated with making the NDR device. An NDR related process recipe includes one or more processing steps associated with effectuating a target peak-to-valley current ratio (PVR) for an NDR device. The processing chamber coupled to the programmable controller is configured to perform at least one semiconductor processing operation on the silicon wafer based on the NDR related process recipe. The semiconductor processing operation can be varied within the processing chamber to achieve a PVR value that varies between a first value, and a second value that is at least twice the first value.
In other embodiments, the PVR value can be varied between 10 and 100 in the semiconductor processing apparatus. The process chamber can be an implanter, an RTA chamber, a deposition reactor, a deposition chamber, etc.
Other aspects of the invention concern different types of optimizations for charge trap profiling for charge trap devices, including NDR devices.
In an NDR FET embodiment, counter-doping is performed to improve a threshold voltage. Thus, a semiconductor device having a control gate, a source region, and a drain region is formed using the steps of: providing a substrate having a first type of conductivity; forming a channel between the source and drain region for carrying the charge carriers between the source and drain regions; the channel is doped in two separate operations such that: during a first channel doping operation the channel is doped with first channel impurities that also have the first type of conductivity; during a second channel doping operation the channel is counter-doped with second channel impurities that have a second type of conductivity. The second type of conductivity is opposite to the first type of conductivity. As a result of the first channel doping operation and the second channel doping operation the channel region as formed has a net first type of conductivity. A charge trapping region that has an interface with the channel is also formed. The charge trapping region has charge trapping sites which temporarily trap charge carriers along the interface and permit the device to operate with a negative differential resistance characteristic. The charge trapping sites are derived at least in part from the first channel impurities forming a charge trap distribution that is substantially concentrated at the interface.
In a preferred embodiment, Arsenic is used for the second channel doping operation, while Boron is used for the first channel doping operation. While silicon is used as a preferred substrate, other substrates could be used, such as SOI, strained Si, SiC, etc. Moreover, different crystal orientation variants of silicon (111, 100, 110) may result in different charge trapping characteristics.
The charge trapping region is typically formed as part of gate insulator for the semiconductor device. In other variations, the charge traps can be directly implanted through a gate insulator after the latter is completed. In still further variants, the charge traps can be formed as part of a two layer trapping region, such as would be derived from a combined thermal oxide and deposited oxide.
In other variations, the charge trapping region can be engineered to not extend throughout an entire length of the interface with the channel. In other instances, the charge trapping region extends from a source region to enhance source side trapping. In still other embodiments, trapping sites are distributed unevenly along the interface to effectuate a variable trapping rate for the energetic carries along the interface. A trapping rate can also be controlled in some instances, so that it varies substantially proportional to a distance along the interface, and/or is preferentially greater in one region over anotherxe2x80x94i.e., such that in a source region it is greater than that near a drain region.
In other embodiments, the charge trapping sites are formed in two distinct operations. For example, an implant operation is used for forming a first set of charge trapping sites, and a heat treatment operation (such as in an steam ambient) forms a second set of charge trapping sites. In still other embodiments, different implants could be used of the same species, or different atomic species to create different types of charge traps (i.e., such as Boron and silicon or metal nanoparticles).
A further related aspect of the invention concerns using annealing operations to help ensure that impurities are preferentially concentrated at an interface, where they can form appropriate trap sites. This is achieved by forming a silicon based negative differential resistance (NDR) semiconductor device with the steps of: providing a substrate; and forming a channel region for carrying a current of charge carriers for the silicon based NDR semiconductor device; and implanting first impurities into the channel region; and forming a first dielectric layer that has an interface with the channel; and annealing the channel region to reduce implantation defects and distribute the first impurities so as to concentrate them along the interface with the channel. The first impurities as distributed along the interface form charge trapping sites with an energy level adapted for temporarily trapping the charge carriers to effectuate an NDR characteristic.
In a preferred embodiment, the first impurities have a first conductivity (p) type that is the same as the substrate. The silicon based NDR semiconductor device is typically a field effect transistor (FET), but can include other charge trap based NDR devices.
In still another variant, additional annealing operations can be performed to further enhance a trap distribution. Thus, this implementation involves performing a plurality of separate annealing operations on the semiconductor structure, wherein at least a first one of the separate annealing operations is adapted so as to distribute and concentrate the carrier trapping sites along an interface with the transistor channel region and with a reduced concentration in a bulk region of the trapping layer. Later separate annealing operations are adapted to alter a concentration and/or arrangement of the charge trapping sites along the interface.
A further related aspect, therefore, concerns a silicon based field effect transistor (FE) comprising a trapping layer proximate to a transistor channel region for the FET, the trapping layer including a carrier trapping sites configured for trapping and de-trapping carriers from the channel region. The carrier trapping sites are distributed such that a concentration of the carrier trapping sites in a bulk region of the trapping layer is at least one order of magnitude less than it is along an interface with the transistor channel region. In this fashion, the FET can exhibit negative differential resistance as a result of the trapping and de-trapping of carriers.
In a preferred embodiment, a concentration of the carrier trapping sites at the interface per cubic centimeter is at least two orders of magnitude greater than a concentration of the carrier trapping sites within the bulk region of the trapping layer. Furthermore, the concentration of an impurity per cubic centimeter used for the carrier trapping sites is at least two times higher at a trapping layer-channel interface than in the channel region.
Another aspect of the invention concerns forming different types of NDR devices on the same substrate. This basically includes the steps of forming a first silicon-based NDR device having a first NDR characteristic on a first portion of the substrate; and forming a second silicon-based NDR device having a second NDR characteristic on a second portion of the substrate. To accommodate different types of circuits, the first NDR characteristic and the second NDR characteristic are substantially different and are used in a first silicon based processing circuit and a separate second silicon based processing circuit respectively.
The first NDR characteristic includes a first peak-to-valley ratio (PVR) and/or a first onset voltage, and the second NDR characteristic includes a second PVR, and/or a second onset voltage. By varying these features, different performances can be achieved for different NDR based circuits.
In one embodiment, PVR/VNDR values are different because a first silicon based processing circuit corresponds to a logic circuit and the second silicon based processing circuit corresponds to a memory circuit.
In another embodiment, PVR/VNDR values are different because the first silicon based processing circuit operates at a first frequency and the second silicon based processing circuit operates at a second frequency greater than the first frequency.
In other embodiments, PVR/VNDR values are different because the first silicon based processing circuit corresponds to a first memory circuit operating with a first operating power requirement and the second silicon based processing circuit corresponds to a second memory circuit operating at a second operating power requirement that is greater than the first operating power requirement.
In still other embodiment, PVR/VNDR values are different because the first silicon-based NDR device is a first field effect transistor (FET) with a first voltage threshold and a first gate length, and the second silicon-based NDR device is a second FET with a second voltage threshold and a second gate length that are substantially different from the first voltage threshold and the first gate length respectively.
The different PVR/VNDR values can be achieved using a first trap distribution and a second charge trap distribution formed for the first silicon-based NDR device and the second silicon-based NDR device respectively. To form such distributions, one approach is form the first trap distribution by a first mask and a first impurity implantation into a first NDR region, and the second charge trap distribution is then formed by a second mask and a second impurity implantation into a second NDR region.
A further related aspect concerns a method of forming multiple a negative differential resistance (NDR) device, including the steps of: forming a first gated silicon-based NDR element and a second gated silicon-based NDR element; setting a peak-to-valley ratio (PVR) characteristic of the first gated silicon-based NDR element to a first target PVR value; setting a PVR characteristic of the second gated silicon-based NDR element to a second target PVR value. The first PVR value and the second PVR value are set to different values during manufacturing of the NDR device to provide different NDR characteristics for the first gated silicon-based NDR element and the second gated silicon-based NDR element.
The first gated silicon-based NDR element and the second gated silicon-based NDR element are preferably formed using metal oxide semiconductor (MOS) compatible processing operations, and can include either NDR FETs, NDR diodes, or other NDR elements which include a tunable PVR characteristic. Using processes described herein, the PVR values can be easily made to vary by at least 50%, 100%, or even 1000%. In a typical application, the first NDR element is used in a memory circuit, and the second NDR element is used in a logic circuit, because different PVRs might be used in such applications.
A related aspect concerns a method of operating different types of negative differential resistance (NDR) devices in an integrated circuit, comprising the steps of: operating a first circuit in the integrated circuit using a first silicon-based NDR device having a first NDR characteristic; and operating a second circuit in the integrated circuit using a second silicon-based NDR device having a second NDR characteristic. Again, the first NDR characteristic and the second NDR characteristic are substantially different so that the first circuit and the second circuit are caused to operate with substantially different electrical characteristics.
To achieve different NDR characteristics, it is not necessary in such embodiments to pre-manufacture different nominal NDR values. Instead, the substantially different electrical characteristics can be achieved by using a first clock frequency and/or activity factor for the first circuit and a second clock frequency and/or activity factor used by the second circuit, and such that the first clock frequency and/or activity factor and the second clock frequency and/or activity factor are substantially different. Alternatively, the substantially different electrical characteristics could include a first gate bias voltage used by the first circuit and a second gate bias voltage used by the second circuit, such that the first gate bias and the second gate bias are substantially different voltages. Another approach is to set the substantially different electrical characteristics to include a first current level used by the first circuit and a second current level used by the second circuit, such that the first current level and the second current level are substantially different currents.
A semiconductor based circuit including two different types of NDR circuits thus comprises a first silicon-based NDR device having a first NDR characteristic on a first portion of a substrate of the semiconductor based circuit; and a second silicon-based NDR device having a second NDR characteristic on a second portion of the substrate. Again, the first NDR characteristic and the second NDR characteristic are substantially different and are used in a first silicon based processing circuit and a separate second silicon based processing circuit respectively on the semiconductor based circuit.
In one preferred approach, the different NDR characteristics are achieved by tailoring a first charge trapping region associated with the first silicon-based NDR device and a second charge trapping region associated with the second silicon-based NDR device.
In some applications, at least one of the first silicon-based NDR device and the second silicon-based NDR device is an NDR FET. Another of such devices can include a silicon based tunnel diode.
Another aspect of the invention pertains to an adaptive NDR device. This is achieved by operating the adaptive silicon-based NDR device with a first current-voltage relationship during a first time period; and operating the adaptive silicon-based NDR device with a second current-voltage relationship during a second time period. The first current-voltage relationship and the second current-voltage relationship NDR characteristic are sufficiently different so as to permit the adaptive silicon based NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively. The adaptive silicon-based NDR device is switched between the first operational mode and the second operational mode in response to a control signal generated by a control circuit on the integrated circuit.
Generally speaking, the operating characteristics of the device are exploited by virtue of the fact that in the first operational mode the adaptive silicon based NDR device switches between a first peak NDR current and a first valley NDR current faster than the adaptive silicon NDR device switches between a second peak NDR current and a second valley NDR current in the second operational mode.
Preferred embodiments of the invention are implemented so that the first current voltage relationship and the second current-voltage relationship can be caused by a variety of operating parameters, such as by applying a first gate bias potential and a second gate bias potential respectively to a gate terminal of the silicon based NDR device; and/or applying a first gating signal at a first clocking frequency and a second gating signal at a second clocking frequency respectively to the adaptive silicon based NDR device.
In some embodiments, the control signal is based on a power consumption mode/speed mode used in the integrated circuit, such that during the first operational mode the adaptive silicon based NDR device consumes less power (or operates more slowly) than during the second operational mode.
In memory cell embodiments, the control signal is a read/write command such that the first operational mode is related to a read or write operation, and the second operational mode is related to a quiescent storage operation. In logic circuits, the first operational mode is related to a normal power mode operation, and the second operational mode is related to a low power mode operation.
Other related aspects pertain to specifically altering (adjusting) a PVR for a circuit, so that an adaptive circuit is implemented. This is done by operating an adaptive NDR element with a first peak-to-valley ratio (PVR) during a first period in which the circuit is performing a processing operation; and operating the adaptive NDR element with a second PVR during a second period in which the circuit is not performing a processing operation, so as to reduce a current consumed by the adaptive NDR element. The first PVR can be controlled to be at least 50% greater than the second PVR, so that a peak-to-valley ratio (PVR) characteristic of the adaptive NDR element is adaptable to an operational requirement of the circuit.
In some embodiments, the circuit is a logic circuit, and the processing operation is a BOOLEAN logic function, such as an AND, NAND, OR, NOR, XOR, XNOR or NOT operation. In other embodiments, the circuit is a memory cell, and the processing operation is an access operation for a data value stored in the memory cell.
A related aspect of this of course is a method of making an adaptive semiconductor circuit. This includes generally forming a silicon-based adaptive NDR device which can operate with a first current-voltage relationship during a first time period and a second current-voltage relationship during a second time period. The first current-voltage relationship and the second current-voltage relationship are defined to be sufficiently different (i.e., differentiable by other circuitry in the system in a usable fashion) so as to permit the silicon based adaptive NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively. A control circuit is then formed for switching the silicon-based adaptive NDR device between the first operational mode and the second operational mode.
In a preferred embodiment, a nominal peak-to-valley current ratio (PVR) is set in the silicon-based adaptive NDR device during a manufacturing procedure. The nominal PVR can be adjusted by the control circuit, resulting in a dynamic, or adaptive PVR value.
In other variants, different adaptive NDR devices can be formed to have different adaptive PVR values. In some instances, of course, they may have a common nominal PVR value for simplifying manufacturing.
A semiconductor circuit that has adaptive behavior includes an adaptive silicon-based NDR device which is adapted to operate with a first current-voltage relationship during a first time period and a second current-voltage relationship during a second time period. As before, the first current-voltage relationship and the second current-voltage relationship NDR characteristic are sufficiently different so as to permit the adaptive silicon based NDR device to have two distinct operational modes, including a first operational mode and a second operational mode respectively. A control circuit for switching the adaptive silicon-based NDR device between the first operational mode and the second operational mode coordinates the PVR transitions. In some instances, different control circuits for different types of NDR devices can be employed.
Still other aspects of the invention pertain to testing and stressing NDR devices, either as a way to enhance their reliability, and/or as a technique for improving actual operational parameters, such as switching speed. This can be done during or after manufacturing operations are completed, and in some cases, even in the field.
Thus, a first method of making a semiconductor device according to this aspect of the invention comprises the steps of: forming a charge trapping region for the semiconductor device during a first manufacturing operation; forming charge traps in the charge trapping region during a sequence of second manufacturing operations, including introducing and distributing impurities within the charge trapping region in a first distribution and a first concentration; applying activation energy to the semiconductor device after the traps are completed to cause a stress current to flow in the semiconductor device, the stress current being adapted to permanently increase the first concentration of charge traps and/or permanently alter the first distribution charge traps in the charge trapping region. In this manner, an operational performance of a charge trap device can be improved in many instances, because new traps, or traps closer to an interface, can be exploited for operation of such devices.
In a preferred embodiment, the semiconductor transistor device is a negative differential resistance device, such as a field effect transistor adapted with a negative differential resistance characteristic. The activation energy is applied as an electrical bias to source, gate and drain regions of a field effect transistor (FET) to cause the stress current to flow in a channel of the FET. The stress current has a relatively high concentration of hot electrons. The hot electrons in turn create additional charge traps near an interface of the channel, and these traps are also engineered with an energy that is suited for only temporarily storing charge. The number of hot electrons, and their energy level, can be controlled precisely for any particular application.
In this fashion, an NDR PVR value, an onset voltage value, and/or a switching speed can be altered for an NDR device, even after manufacturing is completed. Given the nature of certain embodiments of the invention, it is even possible for certain NDR devices to improve in the field with use over time.
The embodiments can further take many other forms as concerns when the activation energy is applied. For example, in some cases, it is applied before an integrated circuit containing the semiconductor transistor device has completed all manufacturing operations. In other cases (or in addition) it can be applied at the end of manufacturing operations.
Further specifics of the testing process are also part of this aspect of the inventions, such as applying the activation energy based on a number of cycles and/or a period of time. Changes in electrical characteristics of the semiconductor device are then monitored. Depending on the results, the stress current is terminated or continued, in some instances with a higher activation energy. In fact, the stress current can be increased in a step-wise manner until a maximum stress current is imposed on the semiconductor device.
A related aspect therefore concerns a method of making a pre-stressed NDR devices as follows: forming a channel on a substrate for the NDR transistor device; and forming a charge trapping region proximate to the channel, the charge trapping region including a number of charge trapping sites distributed throughout the charge trapping region. Again, the charge trapping sites are configured with a trap concentration and trap distribution so that during normal operation of the semiconductor transistor device a first number of energetic carriers in the channel can be temporarily trapped to provide a negative differential resistance characteristic for the semiconductor transistor device. Thereafter, the semiconductor device is stressed before it is placed into normal operation so as to increase the first number of energetic carriers in the channel beyond that which would be present during the normal operation. This stressing step results in an increase to the trap concentration and/or an alteration to the trap distribution in the charge trapping region before the semiconductor transistor device has completed manufacturing operations.
In still other embodiments, the concentration of charge trapping sites occurs even during normal operation of the semiconductor transistor device in the field to alter an NDR characteristic. This can result in improved switching time for the semiconductor transistor device even after manufacturing is otherwise completed.